Intel 18-Core Haswell-EP Xeon E5 v3 Preview
First, the chips and platform:
Collectively, this is a huge leap forward for the entire Xeon E5 series. The Xeon E5 v2 chips, which were based on Ivy Bridge, topped out at 12 cores per socket. The new Xeon E5 v3 cores, in contrast, are going to push as high as 18 cores per socket — a 50% improvement. The TDP range is pushing slightly outwards in both directions; the Xeon E5 v2 family ranged from 50W to 150W, whereas the Xeon E5 v3 family will span 55W – 160W in a single workstation configuration.
The core technologies Intel is introducing to the Xeon E5 v3 family will be familiar to anyone who has read our Haswell coverage — the Haswell architecture doubled certain cache bandwidths, improved overall IPC by a small amount, and introduced features like AVX2, which offers a theoretical near-doubling of floating point performance over the original AVX instructions.
AVX2 hasn’t exactly set the world on fire since it shipped more than a year ago, simply because most consumer software doesn’t see a tremendous benefit from its capabilities. In the world of HPC applications, database processing, and other enterprise tasks, however, this may be different. Scientific computing workloads, at the least, are likely to benefit.
Also new this time around — Full support for DDR4, albeit in rather limited fashion. Exactly how much DDR4 you can use per socket will depend on the clock speed you want to utilize, and while that’s always been the case with modern DRAM, the restrictions on these systems are fairly tight. DDR4-1866 will only allow two DIMMs per channel (the old Xeon v2 processors could handle three DDR3 DIMMS per channel at 1866MHz. This could be a downside for companies that need to maximize both bandwidth and RAM capacity — we’ll have to wait and see. Other features include integrated USB 3.0 support, a full suite of SATA 6G ports, and up to four 10 GigE ports.
The HPC benchmark improvements are considerable between the two CPU families. Power consumption and system efficiency are a critical component of HPC buildouts, particularly as system builders eye the exascale goal — Intel believes DDR4 will provide a long-term significant improvement over DDR3 as well. The figures below assume that three DIMMs per channel are used in both DDR3 and DDR4 configurations.
These kinds of improvements are critical if we’re going to hit exascale level power consumption requirements, even if the shift to DDR4 is only one small step down a very long road.
Flip the page, and we’ll look a bit at workstation performance.